AP210ed2 conformance classes and conformance options

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See also AP203ed2 conformance classes and conformance options.

Different conformance options will be of interest to System Integrators and to Application Developers and to End-Users, as they range from very domain specific such as "System wiring definition" which a System Integrator might specify or "Thickened face solid" which an Application Developer might specify as a derived requirement. The standard includes detailed descriptions (which are not repeated herein) of the conformance options.

List of AP 210 clause number, the conformance option described in that clause and where applicable, links to the supported scope section of the AP.

  • 6.2.1 Activity (co1)
  • 6.2.2 Advanced boundary representation (co2)
  • 6.2.3 Alias identification (co3)
  • 6.2.4 Alternate product and assembly component substitution (co4)
  • 6.2.5 Approval (co5)
  • 6.2.6 Assembly with shape (co6)
  • 6.2.7 Assembly with usage dependent shape of components (co7)
  • 6.2.8 Assignment of a delay between two packaged nodes to the component implementing the path in an assembly (co8)
  • 6.2.9 Assignment of a packaged node to the component implementing the node in an assembly (co9)
  • 6.2.10 Associative draughting (co10)
  • 6.2.11 Basic assembly (co11)
  • 6.2.12 Basic callout without associativity (co12)
  • 6.2.13 Basic classification (co13)
  • 6.2.14 Basic document (co14)
  • 6.2.15 Basic product property (co15)
  • 6.2.16 Basic text and curve presentation (co16)
  • 6.2.17 Cable interface model (co17)
  • 6.2.18 Certification (co18)
  • 6.2.19 Colours and layers (co19)
  • 6.2.20 Complex product property (co20)
  • 6.2.21 Component black box model (co21)
  • 6.2.22 Component footprint definition (co22)
  • 6.2.23 Component functional modifications (co23)
  • 6.2.24 Component package model (co24)
  • 6.2.25 Component package model in a 2D context (co25)
  • 6.2.26 Component package model in a 3D context (co26)
  • 6.2.27 Component package model with corresponding 2D and 3D contexts (co27)
  • 6.2.28 Component package modifications (co28)
  • 6.2.29 Component physical modifications (co29)
  • 6.2.30 Component white box model for analysis (co30)
  • 6.2.31 Composite materials (co31)
  • 6.2.32 Compound shape representation (co32)
  • 6.2.33 Connector model (co33)
  • 6.2.34 Constructive solid geometry 3d (co34)
  • 6.2.35 Construction geometry (co35)
  • 6.2.36 Contract and project (co36)
  • 6.2.37 Curve swept solid (co37)
  • 6.2.38 Date and time (co38)
  • 6.2.39 Document structure and properties (co39)
  • 6.2.40 Edge based wireframe (co40)
  • 6.2.41 Effectivity (co41)
  • 6.2.42 Elementary boundary representation (co42)
  • 6.2.43 Enhanced assembly (co43)
  • 6.2.44 Electrical network model (co44)
  • 6.2.45 Electrotechnical assembly component placement requirements (co45)
  • 6.2.46 Electrotechnical assembly design model in a 2D context (co46)
  • 6.2.47 Electrotechnical assembly design model in a 3D context (co47)
  • 6.2.48 Electrotechnical assembly design model manufacturing features (co48)
  • 6.2.49 Electrotechnical assembly design model physical elements requirement allocation (co49)
  • 6.2.50 Electrotechnical assembly design model with cable included in a 2D context (co50)
  • 6.2.51 Electrotechnical assembly design model with cable included in a 3D context (co51)
  • 6.2.52 Electrotechnical assembly design model with component die bond wire mapping included (co52)
  • 6.2.53 Electrotechnical assembly design model with component die bond wire mapping included in a 2D context (co53)
  • 6.2.54 Electrotechnical assembly design model with component die bond wire mapping included in a 3D context (co54)
  • 6.2.55 Electrotechnical assembly design model with component grouping (co55)
  • 6.2.56 Electrotechnical assembly design model with discrete connector included (co56)
  • 6.2.57 Electrotechnical assembly design model with edge based component mounting (co57)
  • 6.2.58 Electrotechnical assembly design model with explicit electrical subassembly (co58)
  • 6.2.59 Electrotechnical assembly design model with discrete wiring (co59)
  • 6.2.60 Electrotechnical assembly design model with layered interconnect included (co60)
  • 6.2.61 Electrotechnical assembly design model with interface component (co61)
  • 6.2.62 Electrotechnical assembly design model with macros (co62)
  • 6.2.63 Electrotechnical assembly design model with shields (co63)
  • 6.2.64 Electrotechnical assembly design model with stacked component mounting (co64)
  • 6.2.65 Electrotechnical assembly extracted network model (co65)
  • 6.2.66 Electrotechnical assembly functional interface requirement (co66)
  • 6.2.67 Electrotechnical assembly interface model using discrete connections (co67)
  • 6.2.68 Electrotechnical assembly interface model using a printed connector (co68)
  • 6.2.69 Electrotechnical assembly macro model (co69)
  • 6.2.70 Electrotechnical assembly network model (co70)
  • 6.2.71 Electrotechnical assembly panel model (co71)
  • 6.2.72 Electrotechnical assembly physical interface model requirement allocation (co72)
  • 6.2.73 Electrotechnical assembly technology (co73)
  • 6.2.74 Event and time interval (co74)
  • 6.2.75 Extended classification (co75)
  • 6.2.76 Extended geometric tolerance and datum symbols (co76)
  • 6.2.77 External library (co77)
  • 6.2.78 External model (co78)
  • 6.2.79 Faceted boundary representation (co79)
  • 6.2.80 Functional network interface model (co80)
  • 6.2.81 Functional network model (co81)
  • 6.2.82 Functional network mapping to design network (co82)
  • 6.2.83 Functional network mapping to electrotechnical assembly design network (co83)
  • 6.2.84 Functional network mapping to interconnect design elements (co84)
  • 6.2.85 Functional network mapping to layered interconnect internal routing network (co85)
  • 6.2.86 Functional specification (co86)
  • 6.2.87 Geometric placement within physical breakdown elements (co87)
  • 6.2.88 GD&T presentation (co88)
  • 6.2.89 GD&T presentation with association (co89)
  • 6.2.90 GD&T representation (co90)
  • 6.2.91 Geometrically bounded surface (co91)
  • 6.2.92 Geometrically bounded wireframe (co92)
  • 6.2.93 Information rights (co93)
  • 6.2.94 Interconnect interface model (co94)
  • 6.2.95 Layered interconnect complex template (co95)
  • 6.2.96 Layered interconnect design model component placement requirements (co96)
  • 6.2.97 Layered interconnect design layer manifold surface shape (co97)
  • 6.2.98 Layered interconnect design model (co98)
  • 6.2.99 Layered interconnect design model electrical features (co99)
  • 6.2.100 Layered interconnect design model elements requirement allocation (co100)
  • 6.2.101 Layered interconnect design model geometric dimensioning and tolerancing (co101)
  • 6.2.102 Layered interconnect design model manifold surface shape (co102)
  • 6.2.103 Layered interconnect design model manufacturing assembly features (co103)
  • 6.2.104 Layered interconnect design model manufacturing test features (co104)
  • 6.2.105 Layered interconnect design model mechanical features (co105)
  • 6.2.106 Layered interconnect design model with embedded discrete components (co106)
  • 6.2.107 Layered interconnect design model with layer position in a 2d context (co107)
  • 6.2.108 Layered interconnect design model with layer position and located thickness in a 2d context (co108)
  • 6.2.109 Layered interconnect design model with layer position in a 3d context (co109)
  • 6.2.110 Layered interconnect design model with layer position and located thickness in a 3d context (co110)
  • 6.2.111 Layered interconnect design model with macros (co111)
  • 6.2.112 Layered interconnect design model with microwave components in a 2D context (co112)
  • 6.2.113 Layered interconnect design model with microwave components in a 3D context (co113)
  • 6.2.114 Layered interconnect design model with printed components in a 2D context (co114)
  • 6.2.115 Layered interconnect design model with printed components in a 3D context (co115)
  • 6.2.116 Layered interconnect design model with Shield (co116)
  • 6.2.117 Layered interconnect design network model (co117)
  • 6.2.118 Layered interconnect extracted network model (co118)
  • 6.2.119 Layered interconnect fabrication requirement (co119)
  • 6.2.120 Layered interconnect fabrication technology (co120)
  • 6.2.121 Layered interconnect interface model (co121)
  • 6.2.122 Layered interconnect interface model connection zones (co122)
  • 6.2.123 Layered interconnect material stackup design model (co123)
  • 6.2.124 Layered interconnect material stackup fabricator model (co124)
  • 6.2.125 Layered interconnect material stackup library model (co125)
  • 6.2.126 Layered interconnect macro definition (co126)
  • 6.2.127 Layered interconnect panel model (co127)
  • 6.2.128 Manifold subsurface (co128)
  • 6.2.129 Manifold surface (co129)
  • 6.2.130 Materials (co130)
  • 6.2.131 Mechanical design geometric presentation (co131)
  • 6.2.132 Mechanical design presentation representation with draughting (co132)
  • 6.2.133 Mechanical design shaded presentation (co133)
  • 6.2.134 Modified swept solid (co134)
  • 6.2.135 Multi linguism (co135)
  • 6.2.136 Non manifold surface (co136)
  • 6.2.137 Part feature grouping (co137)
  • 6.2.138 Part make from relationship (co138)
  • 6.2.139 Partial document and structured text representation (co139)
  • 6.2.140 Person and organization (co140)
  • 6.2.141 Physical and functional breakdown (co141)
  • 6.2.142 Physical and keepout model shape classification (co142)
  • 6.2.143 Physical interface model (co143)
  • 6.2.144 Physical design model (co144)
  • 6.2.145 Physical design model manifold surface shape (co145)
  • 6.2.146 Physical layer protocol model (co146)
  • 6.2.147 Physical network topology model (co147)
  • 6.2.148 Planned and evaluated characteristics (co148)
  • 6.2.149 Predefined part feature functional classification (co149)
  • 6.2.150 Printed element template model (co150)
  • 6.2.151 Product class and specification (co151)
  • 6.2.152 Product concept (co152)
  • 6.2.153 Product configuration (co153)
  • 6.2.154 Product marking (co154)
  • 6.2.155 Product version relationship (co155)
  • 6.2.156 Rules (co156)
  • 6.2.157 Requirement (co157)
  • 6.2.158 Requirement allocation to functional network element (co158)
  • 6.2.159 Saved view (co159)
  • 6.2.160 Security classification (co160)
  • 6.2.161 Sequential laminate assembly model (co161)
  • 6.2.162 Shape feature (co162)
  • 6.2.163 Shape validation property (co163)
  • 6.2.164 Shell based wireframe (co164)
  • 6.2.165 Simulation model template definition and application (co165)
  • 6.2.166 Software (co166)
  • 6.2.167 Solid with local modification (co167)
  • 6.2.168 Solid with construction history (co168)
  • 6.2.169 Solutions for physical and functional breakdown (co169)
  • 6.2.170 Specification control (co170)
  • 6.2.171 Swept solid (co171)
  • 6.2.172 System wiring definition (co172)
  • 6.2.173 Technical drawing (co173)
  • 6.2.174 Technical drawing with pictures (co174)
  • 6.2.175 Template 3D model shape (co175)
  • 6.2.176 Template and keepout model shape classification (co176)
  • 6.2.177 Template model (co177)
  • 6.2.178 Template model manifold surface shape (co178)
  • 6.2.179 Test requirement allocation (co179)
  • 6.2.180 Text with specified font (co180)
  • 6.2.181 Thermal network model (co181)
  • 6.2.182 Thickened face solid (co182)
  • 6.2.183 Unpackaged semiconductor device interface model (co183) for AP210_Scope#bare_semiconductor_device_specific_data:
  • 6.2.184 Work organization (co184)
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